When you are using the Avalon® streaming configuration scheme, connect this pin to the configuration host.įor other configuration schemes, you can use this pin to monitor the configuration status. This pin is used for synchronization with the configuration host driving nCONFIG and to report errors.Īttention: Ensure that during power up, no external component drives the nSTATUS signal low. If the JTAG interface is not used, connect the TDI pin to the VCCIO_SDM supply using a 1-kΩ resistor.Ĭonfiguration status pin. If the JTAG interface is not used, leave the TDO pin unconnected.ĭedicated JTAG test data input pin located in the SDM bank.Ĭonnect this pin to a 1-kΩ – 10-kΩ pull-up resistor to the VCCIO_SDM supply. If the JTAG interface is not used, connect the TMS pin to the VCCIO_SDM supply using a 1-kΩ resistor.ĭedicated JTAG test data output pin located in the SDM bank. This pin has an internal 20-kΩ pull-up resistor.Ĭonnect this pin to a 1-kΩ – 10-kΩ pull-up resistor to the VCCIO_SDM supply. Connect this pin to the VCCIO_SDM supply using a 10-kΩ pull-up resistor.ĭedicated JTAG test mode select input pin located in the SDM bank. If you plan to use the attestation and/or Black Key Provisioning (BKP) security features, do not connect this pin to GND. In the JTAG daisy-chain mode, the HPS DAP TAP is daisy chained with the SDM mTAP.Ĭonnect this pin through a 1-kΩ pull-down resistor to GND. JTAG clock speed is 22 MHz for JTAG daisy-chain mode. In the JTAG split mode, the SDM JTAG mode is independent of the HPS JTAG.

JTAG clock speed is 33 MHz for JTAG split mode. This pin has an internal 20-kΩ pull-down resistor. This pin supports the 1.8-V single-ended I/O standard.

For more information, refer to the HPS JTAG Pins.

This pin can also be used to access the HPS JTAG chain. Dedicated Configuration/JTAG Pins Pin Nameĭedicated JTAG test clock input pin located in the Secure Device Manager (SDM) bank.

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